module telling_time(m_data,s_data,clk_1khz,rst,beep,speaker);
/*
 * 功能：整点报时
 * m_data: 当前分钟
 * s_data: 当前秒数
 * rst: 复位信号
 * clk_1khz: 输入时钟
 * tellingtime: 输出报时使能
 * Author: xianwu Liang
 */

	output speaker; //输出一个频率
	input clk_1khz;
	input[7:0] m_data,s_data;
	input rst;
	input beep;
	
	wire clk_4hz;
	wire clk_1hz;
	reg[1:0] cnt; //计时器
	reg pusel;
	wire speaker1;
	wire speaker2;
	reg tellingtime;

	//4hz分频
	clok_div_4hz diver_4hz(.clk_1khz(clk_1khz),.clk_4hz(clk_4hz),.rst(rst));
	//1hz分频
	clok_div_1hz diver_1hz(.clk_1khz(clk_1khz),.clk_1hz(clk_1hz),.rst(rst));
 
	always @(posedge clk_4hz or negedge rst) //1s中有1/4脉冲
		if(!rst) begin
			pusel=0;
			cnt = 0;
		end
		else
		begin 
			cnt = cnt + 1'b1; //cnt[1:0]
			if(cnt == 2'b10) pusel=1'b1;
			else pusel = 1'b0;
		end
		
	//倒计时5s
	always @(*)
		if(!rst) tellingtime = 1'b0;
		else if(m_data==8'h59 && s_data > 8'h55) tellingtime = pusel;//倒计时条件开始
		else if(m_data == 8'h00 && s_data == 8'h00) tellingtime = 1'b1; 
		else tellingtime = 0; //报时结束
		
	assign speaker1 = tellingtime?clk_1khz:1'b0;
	assign speaker2 = beep?clk_1khz:1'b0;
	assign speaker = speaker1 || speaker2;
	

endmodule
